The material for forming a capacitor layer according to the present invention comprises a dielectric layer between a first conductive layer to be used for forming a top electrode and a second conductive layer to be used for forming a bottom electrode. Then the first conductive layer and the second conductive layer are processed by etching or the like to form a capacitor circuit. As disclosed in Patent Document 1, the material for forming a capacitor layer is typically used as a material for constituting electronic devices such as printed wiring boards.
The dielectric layer is a material to perform insulating properties and to store certain amounts of electric charges. Various methods are used to form such dielectric layers. In those, a chemical vapor deposition method (CVD method), a sputtering deposition method, and a sol-gel method are popular. For example, Patent Document 2 discloses a method for manufacturing the dielectric layer by the chemical vapor deposition method comprising a step of depositing an amorphous SrTiO3 thin film on a substrate at a temperature less than 400° C.; and a step of subjecting the amorphous SrTiO3 thin film to laser annealing or rapid thermal annealing to crystallize the film to obtain a SrTiO3 thin film. The dielectric layer is obtained by this method for the purpose of obtaining a SrTiO3 thin film having a high dielectric constant.
As for a dielectric layer obtained by the sputtering deposition method, Patent Document 3 discloses a thin film capacitor in which a bottom electrode, a dielectric having a high dielectric constant, and a top electrode are stacked on an arbitrarily layer on a substrate. The thin film capacitor is characterized in that the dielectric having a high dielectric constant is a polycrystal composed of crystal grains and grain boundaries; the polycrystal contains metallic ions capable of having multiple valences as impurities; and the impurities are contained in a higher concentration in the vicinity of the grain boundaries than in the crystal grains of the polycrystal. Patent Document 3 also discloses that the metallic ions capable of having multiple valences are preferably Mn ions. Patent Document 3 describes that thin film capacitors obtained by the method have higher long-term reliability and take a long time for dielectric breakdown.
As for a dielectric layer obtained by the sol-gel method, Patent Document 4 discloses a method for manufacturing a dielectric oxide thin film in which a surface of a substrate is subjected to a hydroxylation treatment and then the dielectric oxide thin film made of metal alkoxide is formed on the substrate. Patent Document 4 describes that a dielectric oxide that can be used for forming the thin film is a metal oxide having the dielectric characteristics such as LiNbO3, Li2B4O7, PbZrTiO3, BaTiO3, SrTiO3, PbLaZrTiO3, LiTaO3, ZnO, or Ta2O5. Patent Document 4 describes that dielectric oxide thin films obtained by the method are excellent in both orientation and crystallinity.
In particular, the formation of a dielectric layer by the sol-gel method disclosed in Patent Document 4 has advantages in comparison with the formation of a dielectric layer by the chemical vapor deposition method (CVD method) or the sputtering deposition method. The advantages are that investments for equipment are not required because vacuum processes are not used and the dielectric layer is easily formed on a substrate having a large area. In addition, it is easy to control the components of the dielectric layer to be in theoretical proportions, and an extremely thin dielectric layer can be obtained. Therefore, the dielectric layer obtained by the sol-gel method is expected to be a material for forming a capacitor layer with large capacitance.    Patent Document 1: National Publication of International Patent Application No. 2002-539634    Patent Document 2: Japanese Patent Laid-Open No. 06-140385    Patent Document 3: Japanese Patent Laid-Open No. 2001-358303    Patent Document 4: Japanese Patent Laid-Open No. 07-294862
However, the dielectric layers obtained by the sol-gel method, the MOCVD method or the sputtering deposition method have some problems, occurrence of a short circuit across a top electrode and a bottom electrode and occurrence of a large leakage current after formation of a capacitor due to its thin thickness of the layer because of uneven film thickness and gaps between oxide particles which result low production yields. Particularly when the areas of electrodes are widened to increase the capacitance of a capacitor, defective products with short circuit may be frequently produced.
In general, capacitor circuits have realized power savings of electronic and electrical equipment and the like by storing excess electricity or the like. Therefore, the capacitor circuits are required to have a capacitance as large as possible, which is a basic requirement on quality. The capacitance (C) of a capacitor is calculated with the formula C=∈·∈0(A/d) (∈0 is a dielectric constant of vacuum). In particular, there has been a recent trend of down sizing of electronic and electrical equipment, and thus down sizing is also demanded for printed wiring boards. Even though a large surface area (A) is allocated for a capacitor electrode in a certain surface area of a printed wiring board or the like, capacitor circuits may be required to have a larger capacitance.
Consequently, a material for forming a capacitor layer comprising a dielectric layer formed by any one of a sol-gel method, an MOCVD method, and a sputtering deposition method which enables manufacturing of the capacitor circuits with large capacitance in high production yields has been required in the market.